1. Technical Field of the Invention
With regard to an input circuit and an output circuit for use in handling the reception and transmission of data signals generated at the time of transmitting data between integrated circuits, the present invention relates, in particular, to an input circuit.
2. Background Art
Generally, this type of input circuit is employed, in particular as a means for receiving data signals, when data is transmitted between different integrated circuits, such as in a transmission circuit of a bus line or the like. In the case of a logical signal transmission, either a high level or low level signal is received. Consequently, in the input circuit, an input terminal for receiving data signals from other integrated circuits, and an output circuit for propagating these data signals within its own integrated circuit invariably exist.
In addition, with regard to the data transmission of a logical signal, a level standard is invariably defined in order discriminate between a high level or low level signal. Consequently, when transmitting data between integrated circuits, it is absolutely necessary to conduct the transmission without disruption of the defined standard regardless of the level. Currently, with regard to a Transistor Transistor Logic (hereafter abbreviated as "TTL") an interface standard which is an example of a data transmission standard, defines the minimum value of a "high level" transmission signal (hereafter abbreviated as "VOHMIN") is defined as 2.4 V. In addition, the maximum value of a "low level" transmission signal (hereafter abbreviated as "VOLMAX") is defined as 0.4 V.
However, in the TTL interface standard, both the maximum value of a "high level" transmission signal (hereafter abbreviated as "VOHMAX") and the minimum value of a "low level" transmission signal (hereafter abbreviated as "VOLMIN") are not stipulated. As a result, almost all of the VOHMAX values reach or approach the maximum value of the integrated circuit power source electric potential, while nearly all of the VOLMIN values reach or approach the minimum value of the integrated circuit ground (earth) electric potential. With respect to the nonspecification of the VOHMAX and VOLMIN, the same can be said for the CMOS interface, which has enjoyed wide use in the recent past. Hence, in a manner similar to the previously described TTL interface, these limiting values generally follow closely the power source electric potential and ground (earth) electric potential of the integrated circuit.
However, a reduction in the power source electric potential supplied to the integrated circuit has accompanied progress in the refinement of the integrated circuit, such that destruction of the components comprising the integrated circuit results from the supply of an unreduced power source electric potential. As a result, reduction of the power source electric potential must accompany the refinement of an integrated circuit. However, it has come to the point where data transmission between integrated circuits possessing different power source electric potentials (e.g., 5 V and 3 V power sources) also occurs.
Still, as in the example of the TTL interface described above, problems in data transmission do not arise as long as the standards for the lowest limits of VOHMIN and VOLMAX are satisfied. However, with regard to VOHMAX in which a standard is particularly undefined, problems arise due to the coexistence of two levels, one approximating the 5 V power source electric potential and another near the level of the 3 V power source.
Hence, as explained above, the supply of, for example, a 5 V power source electric potential to an integrated circuit possessing a 3 V power source results in the destruction of the components of the latter. On the other hand, when an integrated circuit possessing a 3 V power source receives a VOHMAX signal of 5 V or a similar level thereof, destruction of the components comprising the input circuit of the integrated circuit possessing the aforementioned 3 V power source occurs. As a result, a necessity has arisen to allow for the reception of data signals from integrated circuits possessing high power source electric potentials, e.g., 5 V power source, by the input circuit of an integrated circuit possessing a low power source electric potential, e.g., 3 V power source.
Various proposals already exist for an input circuit which is able to receive signal levels which exceed the power source electric potential of its own integrated circuit. Examples of these previous disclosures will be presented in the following.
FIG. 3 shows a conventional example of an input circuit loaded onto a CMOS integrated circuit. In FIG. 3, the drain of NMOS transistor 13 is connected to input terminal 1. The gates of PMOS transistor 4 and NMOS transistor 5 are respectively connected to the source of NMOS transistor 13. In addition, the drains of PMOS transistor 4 and NMOS transistor 5 are respectively connected to output terminal 2. The gate of NMOS transistor 13 and the source of PMOS transistor 4 are respectively connected to power source terminal VDD, with the source of NMOS transistor 5 connected to the ground. In addition, a resistance component 15 is also provided in the figure.
In FIG. 3, a state is initially assumed in which 3 V is supplied to power source terminal VDD, while a high level signal of 5 V is applied to input terminal 1 from another integrated circuit. In this case, since 3 V is supplied to the gate of NMOS transistor 13 while an electric potential of 5 V is supplied to the drain of NMOS transistor 13, the source electric potential of NMOS transistor 13 (currently in a conducting state) is reduced from 3 V by VTN (wherein VTN is the threshold value of NMOS transistor 13) to afford a reduced electric potential.
In this manner, only an electric potential of (3 V-VTN) is imparted to the gate terminals of PMOS transistor 4 and NMOS transistor 5, which thus avoids the destruction of the gate oxide films of these aforementioned PMOS transistor 4 and NMOS transistor 5. In most cases, the threshold value VTN of NMOS transistor 13 is normally set to zero. As a result, an unreduced electric potential of 3 V is supplied to the respective gates of PMOS transistor 4 and NMOS transistor 5. Under these circumstances, PMOS transistor 4 assumes a nonconducting state, with NMOS transistor 5 in a conducting state. Therefore, a converted level which is equal to the low level of the ground electric potential is maintained in output terminal 2, and this level is propagated in an unaltered form to the internal circuitry of the integrated circuit connected to this output terminal 2.
On the other hand, in FIG. 3, the outcome differs when a state is assumed in which 3 V is supplied to power source terminal VDD, while a low level signal equal to the ground electric potential is applied to input terminal 1 from another integrated circuit. In this case, the ground electric potential is applied to the drain of NMOS transistor 13, while an electric potential of 3 V is supplied to the gate of NMOS transistor 13. As a result, the source electric potential of the conducting NMOS transistor 13 is equal to the drain electric potential therein. Hence, a ground electric potential is imparted to the respective gate terminals of PMOS transistor 4 and NMOS transistor 5, such that the destruction of the gate oxide films of these aforementioned PMOS transistor 4 and NMOS transistor 5 does not occur. Under these circumstances, NMOS transistor 5 assumes a nonconducting state, with PMOS transistor 4 in a conducting state. Therefore, a converted level which is equal to the 3 V high level of the electric potential generated by power source terminal VDD is maintained in output terminal 2, and this level is propagated in an unaltered form to the internal circuitry of the integrated circuit connected to this output terminal 2.
However, the first conventional example shown in FIG. 3 has the following two problems. The first problem arises from the extremely large component size of NMOS transistor 13, as well as the large component area of the components comprising the input circuit. Generally, the resistance during conduction of the MOS transistor decreases with increasing gate width. However, in the case of NMOS transistor 13, in the circuit shown in FIG. 3, a high conduction resistance causes a large increase in the time required for a high level to low level conversion, or vice versa, of the electric potential applied to input terminal 1, thus rendering high-speed operation impossible. In addition, this conversion time is proportional to the resistance over the source and drain segment during conduction of NMOS transistor 13. Consequently, it is desirable for the resistance during conduction over the source and drain segment of NMOS transistor 13 to equal the lowest value possible, which in turn requires an enlargement of the gate width of NMOS transistor 13.
The second problem arises in the case when an electric potential value greater than that of power source terminal VDD is applied to input terminal 1 of FIG. 3, such that the electric potential supplied to power source terminal VDD is cut off. In this case, output of a reduced electric potential (VDD-VTN) from the source terminal of NMOS transistor 13 is not possible, which in turn allows the propagation of an electric potential equal to input terminal 1. As a result, the electric potential applied to input terminal 1, which is higher than that of power source terminal VDD, is propagated to the respective gate terminals of PMOS transistor 4 and NMOS transistor 5, thereby causing the destruction of the gate oxide films of these aforementioned transistors.
In order to solve these types of problems, an input circuit has been proposed which applies the BiCMOS integrated circuit technology, an example of which will be described in the following. FIG. 4 represents a second example showing an input circuit which applies the BiCMOS integrated circuit technology. In FIG. 4, the base of a PNP-type bipolar transistor 3 (hereafter abbreviated as "PNP transistor") is connected to input terminal 1. Additionally, the gates of PMOS transistor 4 and NMOS transistor 5, as well as one terminal of resistance component 14, are connected respectively to a collector of PNP transistor 3. The drains of PMOS transistor 4 and NMOS transistor 5 are connected respectively to output terminal 2, while the other terminal of resistance component 14, in addition to the source of PMOS transistor 4 are connected respectively to power source terminal VDD. Also, the aforementioned collector of PNP transistor 3 and source of NMOS transistor 5 are both grounded.
In FIG. 4, a state is initially assumed, as in FIG. 3, in which 3 V is supplied to power source terminal VDD, while a high level signal of 5 V is applied to input terminal 1 from another integrated circuit. In this case, since the segment between the base and emitter of PNP transistor 3 forms a reverse buffer, the electric potential of input terminal 1 is not propagated to the emitter of PNP transistor 3. Consequently, by means of resistance component 14, an electric potential equal to that of power source terminal VDD (i.e., 3 V) is supplied to the respective gates of PMOS transistor 4 and NMOS transistor 5. As a result, the destruction of the gate oxide films of PMOS transistor 4 and NMOS transistor 5 does not occur. Under these circumstances, PMOS transistor 4 assumes a nonconducting state, with NMOS transistor 5 in a conducting state. Therefore, a converted level which is equal to the low level of the ground electric potential is maintained in output terminal 2, and this level is propagated in an unaltered form to the internal circuitry of the integrated circuit connected to this output terminal 2.
On the other hand, in FIG. 4, the outcome differs when a state is assumed in which 3 V is supplied to power source terminal VDD, while a low level signal equal to the ground electric potential is applied to input terminal 1 from another integrated circuit. In this case, the ground electric potential is applied to the base of PNP transistor 3, while an electric potential of 3 V (i.e., the power source electric potential) is supplied to the emitter of PNP transistor 3 via resistance component 14. As a result, PNP transistor 3 assumes a conducting state. Hence, a ground electric potential is imparted to the respective gate terminals of PMOS transistor 4 and NMOS transistor 5, which, in turn, prevents the destruction of the gate oxide films of these aforementioned PMOS transistor 4 and NMOS transistor 5. Under these circumstances, NMOS transistor 5 assumes a nonconducting state, with PMOS transistor 4 in a conducting state. Therefore, a converted level which is equal to the 3 V high level of the electric potential generated by power source terminal VDD is maintained in output terminal 2, and this level is propagated in an unaltered form to the internal circuitry of the integrated circuit connected to this output terminal 2.
The second conventional example shown in FIG. 4 solves the two problems of the first conventional example shown in FIG. 3 in the following manner. In the first conventional example shown in FIG. 3, the components comprising NMOS transistor 13 occupy an area of 11720 .mu.m.sup.2 (117.2 .mu.m.times.100 .mu.m). In contrast, in the second conventional example shown in FIG. 4, PNP transistor 3 and resistance component 14 occupy an area of just 833 .mu.m.sup.2 (17 .mu.m.times.49 .mu.m)--even when including the area separating the two components--which is approximately 7% of the area occupied by NMOS transistor 13.
Here, the gate length and width of NMOS transistor 13 are 1.8 .mu.m and 1272 .mu.m, respectively. Additionally, the emitter area of PNP transistor 3 is 3.times.3 .mu.m.sup.2 with a 10 k.OMEGA. resistance component 14. In this manner, the second conventional example clearly solves the problem of the large area occupied by the components of NMOS transistor 13 of the first conventional example.
In the following, a case will be described, for the example shown in FIG. 4, in which an electric potential greater than that of power source terminal VDD is supplied to input terminal 1, wherein the electric potential supplied to power source terminal VDD is cut off. In this aforementioned state, due to the reverse buffer state that exists between the base and emitter of PNP transistor 3, there is no formation of an electric current route from the input terminal to power source terminal VDD. Consequently, there is no propagation of an electric potential (applied to input terminal 1) which exceeds that of the power source terminal to the gate terminals of PMOS transistor 4 and NMOS transistor 5. In other words, the destruction phenomenon of the gate oxide films of PMOS transistor 4 and NMOS transistor 5 does not occur.
Furthermore, PNP transistor 3 utilizes a lateral PNP transistor which is characterized by large, permanent voltages of approximately 10 to 20 V which can be applied from the base to the emitter, and from the base to the collector. This lateral PNP transistor is also advantageous in that it can be easily manufactured by means of a conventional BiCMOS process.
By means of a construction in which the base of a PNP transistor is connected to input terminal 1 with the emitter of PNP transistor 3 connected between the aforementioned base and the power source terminal VDD via resistance component 14, the aforementioned input circuit according to the second conventional art shown in FIG. 4 prevents the destruction of the gate oxide films of PMOS transistor 4 and NMOS transistor 5 even in the case when, a signal of a higher level than the electric potential of the power source terminal VDD is applied to input terminal 1 with interruption (cut off) of the electric potential of the power source terminal VDD. However, this aforementioned second conventional art poses problems due to the existence of a two electric current routes from the power source terminal VDD to the ground terminal and input terminal, respectively.
To begin with, the first electric current route from the power source terminal VDD to the ground terminal will be explained. In FIG. 4, assuming a state in which a low level is applied to input terminal 1 from another integrated circuit, due to the conducting state of PNP transistor 3, a first electric current route exists between the power source terminal VDD and the ground terminal via resistance component 14. Since the resistance of resistance component 14 is normally set to a value between 1 k.OMEGA. and 10 k.OMEGA., assuming a power source electric potential VDD of 3 V, an electric current of 0.3 mA to 3 mA regularly flows down the aforementioned first electric current route.
In the following, a second electric current route from the power source terminal VDD to the ground terminal will be explained. In FIG. 4, assuming a state in which a low level is applied to input terminal 1 from another integrated circuit, due to the conducting state of PNP transistor 3, a second electric current route exists between the power source terminal VDD and input terminal 1 by means of the forward directional path between the emitter and base of PNP transistor 3. With regard to this PNP transistor, in particular in the case of the aforementioned lateral PNP transistor, generally a small value, a minimum value being (a factor of) 10 or less (note: multiplication factors are used instead of units) for the forward directional current gain is not unusual. Hence, in consideration of dispersion of the manufacturing process, there are times when the minimum value may drop to as low as 1. In the above case, this means that the electric current flowing from the emitter to the collector equals the electric current flowing from the emitter to the base. Thus, in the case of the second conventional example shown in FIG. 4, half of the electric current flowing from the aforementioned power source terminal VDD via the resistance, flows over the path from the base of PNP transistor 3 to the input terminal.
When the aforementioned first electric current route flowing from the power source terminal to the ground via the collector of PNP transistor 3, and second electric current route flowing from the base of PNP transistor 3 towards input terminal 1 exist, the following problems arise. When a first electric current route flowing from the power source terminal to the ground terminal, and a second electric current route flowing from the base of PNP transistor 3 to input terminal 1 exist, the electric power consumed by the integrated circuit, onto which the input circuit is loaded, continues to increase or, alternatively, the calorific value of the integrated circuit increases. Moreover, in order to have quantitative dependency of the input circuits used in the aforementioned integrated circuit, there exists another problem in that the size of the aforementioned requires, in some cases, loading onto a package components of enormous size at great cost.
In addition, in the aforementioned input circuit, there are times when the input terminal enters a nonconducting state wherein neither a high or low level (signal) is applied thereto. In this nonconducting state, it becomes impossible to distinguish between a high level or low level. As a result, the input circuit normally decides to either keep the input terminal at a high level by means of providing a resistance component between the input terminal and power source terminal (hereafter referred to as "pull-up resistance"), or keep the input terminal at a low level by means of providing a resistance component between the input terminal and ground terminal (hereafter referred to as "pull-down resistance"). However, in the case when a voltage greater than that of the power source terminal is applied to the input terminal, application of the pull-down resistance is normally selected since selection of the pull-up resistance results in the unfavorable formation of an electric current route from the input terminal to the power source terminal. In addition, a markedly high resistance (of the resistance component) is used as the pull-down resistance, with a value of approximately 50 k.OMEGA. being the norm.
When applying a pull-down resistance, due to the flow of the electric current, which is coursing over the second electric current route from the power source terminal to the input terminal of the input circuit of the aforementioned second convention art, generation of an electromotive force occurs resulting in drawbacks such as disruption of the original low level and supply of a high level to the input terminal.